A typical communication system, such as that depicted in FIG. 1, comprises a transmitter 101 which sends information bearing signals over a communications channel 103 to a receiver 105. When the signals are defined only at discrete values (e.g., &lt;=0.8 volts and &gt;=3.5 volts) the signals are commonly referred to as "digital signals" (in contrast to "analog signals" which are defined continuously within a given range of values). Traditionally, digital signals are transmitted sequentially: each being sent for a constant amount of time and during a precisely defined interval of time. Typically, the time interval is defined for the transmitter by an electronic metronome known to those skilled in the art as a "clock signal" (hereinafter "clock"). A clock is typically generated by a crystal oscillator and is embodied as electric squarewave signal with constant frequency and a 50% duty cycle. FIG. 2 at 201 shows a waveform illustrative of a clock.
With the beginning of each cycle or "tick" of the clock, one clock period ends (and the transmission of one signal ends) and a second clock period begins (and the transmission of the next signal begins). FIG. 2 at 207 shows a typical waveform for an information bearing signal over time and with respect to clock 201. As is well known, capacitance, inductance and other parasitic effects prohibit the information bearing signal on lead 207 from changing instantaneously from one defined value to another. The signal may assume, therefore, undefined values during the period of transition. FIG. 2 at 213 shows a typical transition from a logical "0" to a logical "1" for the illustrative waveform 207.
To assure that the receiver correctly interprets the incoming signals, the receiver must selectively read the incoming signals only at instants when the signals have stabilized and not when they are undergoing transition. This requires the receiver to know when the incoming signals are stable and when they are not. Advantageously, the receiver also has an electronic metronome, synchronized to the incoming signal which dictates "read now--wait, read now--wait, read now--wait . . . ." Typically, the receiver has information regarding the frequency or frequencies of the transmitter's clock and has a clock with that same frequency. The receiver's clock, however, will, without more, bear no phase relationship to the incoming signal and thus the receiver will have no synchronized metronome to assist it in reading the incoming signal. To generate a clock which is synchronized with respect to the incoming signal, the receiver may advantageously utilize a "clock recovery system".
The phase of the incoming signal may be discerned or "recovered" with a clock recovery system. FIG. 3 shows how a clock recovery system may be used in a receiver to correctly read the incoming signal and to extract the transmitted information. Incoming signal on lead 301 is fed into clock recovery system 311 to generate a periodic waveform 313 or "recovered clock". The incoming signal 301 is also distributed with optional delay to a data extraction device 307. The periodic waveform 313 and the signal 305 are processed in the data extractor 307 to generate the output 309. Data extractor 307 could be as simple as a well-known Master/Slave D flip-flop, with signal 305 connected to the D input of the flip-flop, signal 313 connected to the clock input of the flip-flop and output 309 connected to the Q output of the flip-flop.
At least two clock recovery techniques are currently known. First, the transmitter's clock may be transmitted to the receiver on a communication channel in parallel to the channel carrying the incoming signals. The receiver can then estimate the phase of the incoming signals from the phase of the transmitter's clock. This technique, however, is disadvantageous in that it requires additional hardware (e.g., the extra communication channel) and is subject to phase skew between the transmitted clock and the incoming signal.
Alternately, the phase of the incoming signals may be recovered directly from the incoming signals themselves because the incoming signals carry the information needed to discern its phase. At least two techniques are known which recover the phase of the incoming signals from the incoming signals themselves.
The first is the open-loop clock recovery system representatively taught by I. Dorros et al., An Experimental 224 Mb/s Digital Repeatered Line, The Bell System Technical Journal, Vol. 45, No. 7, pp. 993-1043 (September 1966). Open-loop systems are characterized by a high-Q, narrow bandpass filter (e.g., a SAW filter) yet may be disadvantageous in that they typically require expensive non-integrated components, hundreds of incoming signal transitions to reach steady state and may be susceptible to temperature variations and age.
The second is the closed-loop clock recovery system. A representative closed-loop clock recovery system is taught by R. R. Cordell et al. in A 50 Mhz Phase- and Frequency-Locked Loop, IEEE Journal of Solid State Circuits, Vol. SC-14, No. 6, pp 1003-1010 (December 1979). Closed-loop systems are characterized by a phase-locked loop which attempts to lock onto the phase of the incoming signal. While closed-loop recovery systems are self-adjusting (thus mitigating temperature and aging effects) and can be easily integrated, they are disadvantageous in typically requiring hundreds of incoming signal transitions to reach steady state.
While these clock recovery mechanisms may be satisfactory for signals which carry voice communications, they may be disadvantageous for signals which carry non-voice information.